1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to a semiconductor memory device including a redundancy circuit.
2. Description of the Background Art
In order to increase production yield of semiconductor memory devices, semiconductor memory devices incorporating redundancy circuits have been developed. With use of a redundancy circuit, when a certain word line of a semiconductor memory device or memory cells connected to that word line has any defects, that word line can be replaced with a redundancy word line. Accordingly, the defective word line or defective memory cells can be rescued.
FIG. 7 is a diagram showing structure of a major portion of a conventional semiconductor memory device including a redundancy circuit.
A memory array 1 includes a plurality of word lines WL, a plurality of bit line pairs BL intersecting the plurality of word lines WL, and a plurality of memory cells MC provided at intersections of the word lines and the bit lines. The memory array 1 further includes a redundancy word line RWL. The memory cells MC are also connected to the redundancy word line RWL.
The memory array 1 is connected with a decoder 2 and a sense amplifier unit 13. The sense amplifier unit 13 includes a plurality of sense amplifiers and a plurality of transfer gates connected to the plurality of bit line pairs BL, and a decoder.
This semiconductor memory device incorporates a substitution circuit 10. The substitution circuit 10 includes a redundancy selecting circuit 3, a substitute address program circuit 4 and a NAND circuit 5. The substitution circuit 10 and the redundant word line RWL constitute the redundancy circuit.
An operation of the semiconductor memory device of FIG. 7 will now be described. The decoder 2 responds to an X address signal XA to select one of the plurality of word lines WL in the memory array 1 and raises a potential of the selected word line WL to a logic high level (or a "H" level). Accordingly, data are read from memory cells MC connected to that word line WL to their corresponding bit line pairs BL. amplifiers included in the sense amplifier unit 13. respond to a Y address signal YA to turn one of the plurality of transfer gates on. The data are amplified by the sense amplifiers included in the sense amplifier unit 13. Consequently, one data is output.
When a certain word line WL has some associated defect, the redundancy word line RWL is used in place of the defective word line WL. In that case, an output of the redundancy selecting circuit 3 attains a logic high level. In addition, an address of a word line WL to be substituted is programmed in the substitute address program circuit 4.
When an address designated by the X address signal XA matches the address programmed in the substitute address program circuit 4, i.e., the substitute address, an output of the substitute address program circuit 4 attains a logic high level. When outputs of the redundancy selecting circuit 3 and the substitute address program circuit 4 attain a logic high level, an output of the NAND circuit 5 (a decoder inactivation signal DA) attains a logic low level (or a "L" level). This renders the decoder 2 inactive and brings all the word lines WL in a nonselection state. In addition, the potential of the redundancy word line RWL rises to a logic high level.
In such a manner, if the defective word line WL or the word line WL connected to defective memory cells is selected, then the redundancy word line RWL is selected in place of the selected word line WL.
While the memory array 1 includes a redundancy bit line pair in some case, such a redundancy bit line pair is omitted from FIG. 7.
FIG. 8 is a circuit diagram showing a detailed structure of the redundancy selecting circuit 3. The redundancy selecting circuit 3 includes a fuse 31, a MOS capacitor 32, a high resistor 33, P channel transistors 34 and 35, and an N channel transistor 36.
In a normal state, i.e., where the redundancy word line RWL is not used (redundancy nonselection time), the fuse 31 is in a connection state. Thus, a potential on a node N1 is at a ground level, and a signal of a logic low level is input to the NAND circuit 5 of FIG. 7. Consequently, the decoder inactivation signal DA attains a logic high level, and the potential of the redundancy word line RWL does not rise.
When the redundancy word line RWL is used (redundancy selection time), the fuse 1 is cut off. When a power supply is turned on, the potential on the node N1 rises toward a logic high level because of a current flowing through the high resistor 33 in a case where a supply voltage rises gradually, while the potential on the node N1 rises toward a logic high level because of a capacitance coupling by the MOS capacitor 32 in a case where the supply voltage rises sharply. Further, a positive feedback circuit comprised of the transistors 34, 35 and 36 causes the potential on the node N1 to attain a complete logic high level.
In such a manner, the output of the redundancy selecting circuit 3 attains a logic low level at the redundancy nonselection time, while the output thereof attains a logic high level at the redundancy selection time.
FIG. 9 shows a circuit diagram showing a detailed configuration of the substitute address program circuit 4. A circuit part A includes a fuse 41, a MOS capacitor 42, a high resistor 43, P channel transistors 44 and 45, and an N channel transistor 46. A circuit part B includes a fuse 51, a MOS capacitor 52, a high resistor 53, P channel transistors 54 and 55, and an N channel transistor 56. A structure and operation of the circuit parts A and B is identical to that of the redundancy selecting circuit 3 of FIG. 8.
Thus, a potential on a node N3 in the circuit part A attains a logic low level when the fuse 41 is in a connection state, while the potential on the node N3 attains a logic high level when the fuse 41 is cut off. Similarly, a potential on a node N5 in the circuit part B attains a logic low level when the fuse 51 is in a connection state, while the potential on the node N5 attains a logic high level when the fuse 51 is cut off.
P channel transistors 61 and 62 and N channel transistors 71 and 72 are connected between an input terminal I1 and an output terminal O1. P channel transistors 63 and 64 and N channel transistors 73 and 74 are connected between an input terminal I2 and the output terminal O1. P channel transistors 65 and 66 and N channel transistors 75 and 76 are connected between an input terminal I3 and the output terminal O1. P channel transistors 67 and 68 and N channel transistors 77 and 78 are connected between an input terminal I4 and the output terminal O1.
Respective gates of the transistors 61, 73, 65 and 77 are connected to the node N3 in the circuit part A, while respective gates of the transistors 71, 63, 75 and 67 are connected to a node N4 in the circuit part A. Respective gates of the transistors 62, 64, 76 and 78 are connected to the node N5 in the circuit part B, while respective gates of the transistors 72, 74, 66 and 68 are connected to a node N6 in the circuit part B.
The substitute address program circuit 4 shown in FIG. 9 is a program circuit for X address signals X0 and X1. Description will now be made on a program method in this program circuit.
First, predecode signals X0.X1, X0.X1, X0.X1 and X0.X1 are defined as follows:
X0.X1="H" (i.e., a logic high level) where X0="H", X1="H"; PA1 X0.X1="H" where X0="H", X1="L" (i.e., a logic low level); PA1 X0.X1="H" where X0="L", X1="H"; and PA1 X0.X1="H" where X0="L", X1="L".
Each of the predecode signals X0.X1, X0.X1, X0.X1 and X0.X1 attains a logic low level except for the foregoing conditions.
Assume that the input terminal I1 is coupled with the predecode signal X0.X1, the input terminal I2 with the predecode signal X0.X1, the input terminal I3 with the predecode signal X0.X1, and the input terminal I4 with the predecode signal X0.X1.
When the fuses 41 and 51 are in a connection state, only the input terminal I1 is connected to the output terminal O1. Accordingly, the predecode signal X0.X1 appears on the output terminal O1. An output attains a logic high level when X0="H", X1="H". Since the redundancy word line RWL is selected at that time, an address of X0=X1="H" is programmed into the substitute address program circuit 4 by the fuses 41 and 51.
Similarly, when the fuse 41 is cut off and the fuse 51 is in a connection state, the predecode signal X0.X1 appears on the output terminal O1. Thus, an address of X0="H", X1="L" is programmed. When the fuse 41 is in a connection state and the fuse 51 is cut off, the predecode signal X0.X1 appears on the output terminal O1. Thus, an address of X0="L", X1="H" is programmed. When both the fuses 41 and 51 are cut off, the predecode signal X0.X1 appears on the output terminal O1. Thus, an address of X0=X1="L" is programmed.
Since the number of X address signals is normally two or more, the circuits shown in FIG. 9 are provided in a plural number and an output of each circuit is input to the NAND gate 5 of FIG. 7.
When the memory array 1 is divided into a plurality of memory blocks, a redundancy word line RWL is provided in each memory block. In this case, if there is only one substitution circuit 10 shown in FIG. 7, then only one defect is rescued despite the fact that there are redundancy word lines RWL corresponding in number to the memory blocks.
Thus, when the memory array 1 is divided into a plurality of memory blocks, one substitution circuit 10 is provided for each memory block. As a result, a word line WL in each memory block is replaced by a redundancy word line RWL in the same memory block by its corresponding substitution circuit 10. However, at most two redundancy word lines may be provided in each memory block.
As described above, in the semiconductor memory device including the conventional redundancy circuit, defective memory cells (defective bits) must be replaced by at most two redundancy word lines and redundant bit line pairs provided in one memory block, for rescue of the defective bits.
As a pattern for formation of memory cells becomes more miniaturized, it more frequently occurs that one defect makes a plurality of memory cells defective. It is difficult for at most two redundancy word lines and redundancy bit line pairs to rescue multi-bit defects extending two-dimensionally.
As has been described heretofore, the semiconductor memory device including the conventional redundancy circuit has the disadvantage that the device is not capable of handling an increase of multi-bit defects with miniaturization of the transistor formation pattern.